The present invention relates to test systems for testing integrated circuit devices.
To test high-speed devices, conventional test systems generate multiple high-frequency timing signals in order to format signals for each of the device-under-test (DUT) pins being tested. Each timing signal typically appears as a low-to-high voltage transition (a “rising edge”). The circuitry used to generate these timing signals generally may be divided into two portions: a first portion, called the “timing marker generation circuit” or an “edge generator circuit;” and a second portion, called the “formatter.” The timing marker generation circuit converts data received from a computer processing unit (CPU) to a software word, the software word including information about the time for a timing signal transition (i.e., the “timing marker” or “timing edge”). The formatter applies an edge type (e.g., the rising edge) to inputs of a pin electronics device at a time determined using information contained in the software word.
In a typical test system, the timing generation circuit converts data received from the CPU to software words for transmission to a formatter. The software words indicate a desired output level and the desired timing of the output level. In conventional test systems, the formatter generally is a dedicated resource per DUT pin and drives or strobes the input of a pin electronics (PE) device that is coupled to a DUT pin at a fixed frequency, usually the test system frequency. One can describe a PE device as including electronic buffers and comparators that communicate back and forth with a DUT. The formatter generally includes two complementary formatting circuits—a drive circuit for generating test signals to be applied to inputs of the PE device and a response circuit for receiving the signals from outputs of the PE device coupled to the DUT.
The drive circuit outputs accurate timing edges or formatted signals. The drive circuit outputs certain signals, which may include two formatted signals, such as drive-high (DHI) and drive-inhibit (DINH). For example, a typical drive circuit can output formatted signals DHI and DINH to the PE device. The PE device uses formatted signals DHI and DINH, or similar markers, to determine whether to drive a DUT pin to a predefined logic state, such as high, low, or tri-state.
The response circuit generates timing markers, such as StbHi, StbLo, StbOff, and StbZ, which are used with event type information to strobe signals coming from the PE, such as above comparator high (ACH) and below comparator low (BCL), to determine whether the DUT pin passes or fails a test. If the event type indicates a state different than the actual state of signals ACH and BCL, the response circuit generates and transmits a “fail” signal. The test system then records the data generated by the response circuit, creates a data log and transfers the data to the CPU or to local memory for analysis.
Test systems for testing high-speed integrated-circuit devices, such as microprocessors and microcontrollers, have become increasingly sophisticated due to high-speed requirements. Formatters play a crucial role in establishing the accuracy, and indeed, the functionality of a test system. Evolving system architectures, testing paradigms, and DUT specifications pose new challenges and requirements on the design of timing critical circuitry. Notable among these requirements is the requirement that current and future test systems hardware bring down the total cost of test through better hardware integration and software support. Modern test systems hardware needs to be both modular and flexible.
GaAs or Bipolar technologies are well known to be suited for high-speed (e.g. around 800 Mbps) and high accuracy (less than +/−100 ps edge placement accuracy) timing applications. However the use of GaAs or Bipolar technologies results in a relative increase in hardware costs. Furthermore, the use of these technologies results in a relative increase in system size and power consumption.
On the other hand, CMOS technologies are well known to be suited for low cost, small size and low power applications that do not require highly accurate edge placement (e.g., less than +/−100 ps). Temperature and voltage variation are factors in reduction of edge placement accuracy (EPA) in CMOS. In other words, temperature and voltage variation are examples of timing error factors in CMOS.
As an example of an article addressing the impact of temperature variation on CMOS technology, R. Hägglund and L. Wanhammar, in “Tuning and compensation of Temperature Effects in Analog Integrated Filters,” (listed as being published in Proc. Swedish System-on-Chip Conf, Arild, Sweden, May 20-21, 2001 and incorporated herein by reference in its entirety) discuss tuning strategies for integrated filters and compensation schemes to decrease the temperature dependence of the transconductance value of a differential gain stage. The Hagglund article notes that an increase in temperature causes CMOS transistors to conduct a larger current. Thus, given temperature variations of a specified size, neither the transconductance value nor the drain-source resistance have a constant value and therefore the gain, bandwidth and phase response vary with the temperature, affecting the transfer function.
As another example of an article that discusses attempts to solve timing error factors in CMOS technology, Okayasu, M. Suda, and K. Yamamoto, in “CMOS Circuit Technology for Precise GHz Timing Generator” (listed as being presented on Oct. 9, 2002 at the 2002ITC International Test Conference in Baltimore Md., and incorporated herein by reference in its entirety) discuss CMOS circuit technology for a GHz timing-generator.
Given that bipolar technologies typically result in relatively large system size and power consumption and given that CMOS technology typically does not result in relatively accurate edge placement (e.g., less than +/−100 ps), a need exists for test systems that are suitable for high-speed and high accuracy timing applications and that are low cost and have small size and low power consumption relative to conventional systems.